Tuesday, April 26, 2011

18.14 output voltage dynamics

I am a little confused about the dynamics in problem 18.14.

When we came up with the linearized model for the feedforward boost rectifier in class, we neglected any changes in v_hat and assumed the output voltage to be basically DC. This led to a simple G_id(s) which I used for the current loop in the problem. However, this is not sufficient for the voltage loop of the problem since it is trying to regulate variations in output voltage. Does it make sense to be using a different small signal model to solve the different loops in the circuit? I was thinking about using the same average equations as in 18.3 but assuming that the input current is a perfectly regulated DC signal and deriving a new small signal model from there. Does this approach seem reasonable?

2 comments:

  1. I believe you use the control to output transfer function which is eqn 18.105. When you do this you have to use j2 from table 18.1 and I assume you use the vcontrol from part d to find j2. Hopefully someone else can confirm this.

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  2. Yeah, for the outer (voltage) loop you model the converter as a loss-free resistor, as that's what the much faster current loop forces the dynamics to be. Therefore, you model the output port as a power source. In that model we're not assuming the output voltage is constant, so it should be consistent with the dynamics we're trying to find.

    In other words, the approach you described is exactly what is done in the book, with the assumption that the current loop works perfectly.

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